Adaptive keeper sizing for dynamic circuits based on fused process corner data

ABSTRACT

An invention is provided for an adaptive keeper circuit. The adaptive keeper circuit includes a first keeper transistor having a first terminal in electrical communication with a power supply and a second terminal in electrical communication with an internal dynamic node. In addition, a second keeper transistor is included that is configured in parallel to the first keeper transistor. The second keeper transistor also has a first terminal in electrical communication with the power supply. The second keeper transistor can be added to the first keeper transistor using a feedback bit line, which is configured to control current flow between the second keeper transistor and the internal dynamic node based on a state of the feedback bit line. The state of the feedback bit line is based on a process corner characteristic of the die. Additional keeper transistors and corresponding feedback bit lines can be added to the keeper circuit to increase flexibility.

CROSS REFERENCE TO RELATED APPLICATIONS

[0001] This application is related to U.S. patent application Ser. No.______ (Attorney Docket No. SUNMP120), filed Sep. 17, 2002, and entitled“Process Monitor Based Keeper Scheme For Dynamic Circuits,” which isincorporated herein by reference.

BACKGROUND OF THE INVENTION

[0002] 1. Field of the Invention

[0003] This invention relates generally to keeper circuits, and moreparticularly to adaptive keeper transistor sizing for dynamic circuitsbased on global process corner data.

[0004] 2. Description of the Related Art

[0005] Conventionally, keeper circuits have been utilized in dynamiccircuits to prevent leaking at an internal dynamic node. For example,dynamic wide OR circuits commonly utilized in large register files oftenuse keeper circuits to prevent unintentional discharging of the internaldynamic node, as illustrated in FIG. 1.

[0006]FIG. 1 is a schematic diagram showing a conventional dynamic wideOR circuit 100. The dynamic wide OR circuit 100 includes a prechargep-channel transistor 102, having a first terminal coupled to VDD, asecond terminal coupled to an internal dynamic node 110, and a gatecoupled to a clock signal 108. In addition, a plurality of evaluationtransistors 104 a-104 c is included in the dynamic wide OR circuit 100.Each evaluation transistor 104 a-104 c includes a first terminal coupledto the internal dynamic node 110 and a second terminal coupled to afirst terminal of transistor 106. In addition, the gate of eachevaluation transistor 104 a-104 c is coupled to an input In₀, In₁, andIn₂, respectively. A second terminal of transistor 106 is coupled toground and the gate of transistor 106 is coupled to the clock signal108. Although FIG. 1 illustrates an OR circuit, it should be noted thatthe evaluation transistors can be configured to form any logic circuitas desired by the circuit developer.

[0007] The conventional dynamic wide OR circuit 100 operates in twophases, namely, a precharge phase and an evaluation phase. During theprecharge phase the clock signal 108 is LOW. Hence, transistor 106 isOFF and the precharge transistor 102 is ON, which allows current to flowfrom VDD to the internal dynamic node 110. As a result, a precharge isprovided to the internal dynamic node 110, which goes HIGH. Becausetransistor 106 is OFF, the internal dynamic node 110 stays high duringthe precharge phase regardless of the state of the evaluationtransistors 104 a-104 c.

[0008] During the evaluation phase the clock signal 108 is HIGH. Hence,transistor 106 is ON and the precharge transistor 102 is OFF, whichallows current to flow from the internal dynamic node 110 to groundbased on the state of the evaluation transistors 104 a-104 c. The stateof each evaluation transistor 104 a-104 c depends on the state of theinput In₀, In₁, and In₂ coupled to the gate of the particular evaluationtransistor 104 a-104 c. As can be seen in the example of FIG. 1, whenthe input In₀, In₁, and In₂ of any evaluation transistor 104 a-104 c isHIGH, the evaluation transistor 104 a-104 c turns ON and allows currentto flow from the internal dynamic node 110 to ground through transistor106. As a result, the output 112 will be LOW.

[0009] However, when all the inputs In₀, In₁, and In₂ of the evaluationtransistors 104 a-104 c are LOW, all the evaluation transistors 104a-104 c are OFF and the internal dynamic node 110 is allowed to stayHIGH, resulting in a HIGH at the output 112. Unfortunately, theevaluation transistors 104 a-104 c leak. That is, each evaluationtransistor 104 a-104 c allows a small amount of leakage current to flowto ground through transistor 106 when the evaluation transistor 104a-104 c is OFF. Thus, when all the inputs In₀, In₁, and In₂ of theevaluation transistors 104 a-104 c are LOW, a leakage current is stillallowed to flow from the internal dynamic node 110 to ground thoughtransistor 106. Thus, the voltage on the internal dynamic node 110 fallsover time.

[0010] To combat the leakage current, keeper circuits 114 are utilized.The conventional keeper circuit 114 includes an inverter 118 having aninput coupled to the internal dynamic node 110 and an output coupled tothe gate of a keeper transistor 116. The keeper transistor 116 includesa first terminal coupled to VDD and a second terminal coupled to theinternal dynamic node 110.

[0011] The keeper circuit 114 is primarily utilized to address leakageby keeping the internal dynamic node 110 HIGH when all the evaluationtransistors 104 a-104 c are OFF. In particular, when the internaldynamic node 110 is HIGH, the input of the inverter 118 is HIGH,resulting in a LOW at the output of the inverter 118. The LOW at theoutput of the inverter 118 turns ON the keeper transistor 116, whichallows current to flow into the internal dynamic node 110 from VDD.

[0012] On the other hand, when the internal dynamic node is LOW, becauseof an evaluation transistor 104 a-104 c being ON, the keeper circuit 114turns OFF. Specifically, when the internal dynamic node 110 is LOW, theinput of the inverter 118 is LOW, resulting in a HIGH at the output ofthe inverter 118. The HIGH at the output of the inverter 118 turns OFFthe keeper transistor 116, which prevents current from flowing into theinternal dynamic node 110 from VDD.

[0013] The leakage current is proportional to the size and number ofevaluation devices 104 a-104 c present in the circuit. Hence, the sizeof the keeper transistor 116 is selected based on the size and number ofevaluation devices 104 a-104 c present in the circuit, generally, at theworst case for leakage for expected process, voltage, and temperature.It should be noted that the keeper transistor 116 cannot be madearbitrarily large because the keeper transistor circuit 114 willadversely affect evaluation performance if the keeper transistor 116 istoo large. In particular, if the keeper transistor 116 is too large, thekeeper transistor 116 will try to keep the internal dynamic node 110HIGH when the evaluation transistors attempt to discharge the internaldynamic node 110. As a result, the evaluation time can be increasedand/or the value of the precharged internal dynamic node 110 may notchange when an evaluation transistor is ON.

[0014] Unfortunately, this also imposes a limit on the number ofevaluation devices that can be included in a conventional dynamiccircuit. Increasing the number of evaluation transistors in a dynamiccircuit increases the amount of leakage current proportionally. As aresult, larger keeper transistors 116 are required. However, at somepoint, the size of keeper transistor 116 becomes too large for a singleevaluation transistor 1041-104 c to overcome and pull the internaldynamic node 110 LOW. This point becomes the limit to the number ofevaluation devices that can be included in the dynamic circuit. Thus,the size of the keeper transistor is conventionally selected based onthis limit and the worst-case leakage corner. It is desirable to removethis constraint from the design.

[0015] In view of the foregoing, there is a need for a keeper circuitdesign that allows the effective size of the keeper transistor to bechanged based on the individual properties of the chip. The keepercircuits should adjust the effective keeper transistor size based on therequirements of the overall circuit, such as electrical characteristicsof the transistors utilized in the circuit. As a result, larger dynamiccircuits could be utilized, potentially improving the speed of themicroprocessor itself.

SUMMARY OF THE INVENTION

[0016] Broadly speaking, the present invention fills these needs byproviding adaptive keeper transistor sizing in dynamic circuits based onfused process corner data. In one embodiment, an adaptive keeper circuitis disclosed. The adaptive keeper circuit includes a first keepertransistor having a first terminal in electrical communication with apower supply and a second terminal in electrical communication with aninternal dynamic node. In addition, a second keeper transistor isincluded that is configured in parallel to the first keeper transistor.The second keeper transistor also has a first terminal in electricalcommunication with the power supply. The second keeper transistor can beadded to the first keeper transistor using a feedback bit line, which isconfigured to control current flow between the second keeper transistorand the internal dynamic node based on a state of the feedback bit line.The state of the feedback bit line is based on a process cornercharacteristic of the die. Additional keeper transistors andcorresponding feedback bit lines can be added to the keeper circuit toincrease flexibility.

[0017] In an additional embodiment, a semiconductor die having adaptivekeeper logic is disclosed. The semiconductor die includes a plurality ofdynamic circuits, each including an adaptive keeper circuit that iscapable of being adjusted based on a bit code. A process corner databankis also included that includes process corner data indicating a processcorner of the semiconductor die. In communication with both the processcorner databank and the plurality of dynamic circuits is a testprocessor unit. The test processor unit is capable of obtaining processcorner data from the process corner databank and can further provide abit code based on the process corner data to the plurality of dynamiccircuits. In this manner, the adaptive keeper circuits of the dynamiccircuits can be adjusted based on the process corner data.

[0018] A method for optimizing a keeper circuit for use in a dynamiccircuit is disclosed in a further embodiment of the present invention.The method includes obtaining process corner data for a die from adatabank present on the die. The process corner data then is translatedinto a bit code, which indicates a process corner of the die. In thismanner, particular secondary keeper transistors can be selected to addto the first transistor based on the bit code. Other aspects andadvantages of the invention will become apparent from the followingdetailed description, taken in conjunction with the accompanyingdrawings, illustrating by way of example the principles of theinvention.

BRIEF DESCRIPTION OF THE DRAWINGS

[0019] The invention, together with further advantages thereof, may bestbe understood by reference to the following description taken inconjunction with the accompanying drawings in which:

[0020]FIG. 1 is a schematic diagram showing a conventional dynamic wideOR circuit;

[0021]FIG. 2 is a schematic diagram showing an exemplary dynamic wide ORcircuit, in accordance with an embodiment of the present invention;

[0022]FIG. 3 is a schematic diagram showing a keeper circuit havingthree keeper transistor paths, in accordance with an embodiment of thepresent invention;

[0023]FIG. 4 is a block diagram showing a die having adaptive keepersizing capabilities, in accordance with an embodiment of the presentinvention; and

[0024]FIG. 5 is a block diagram showing a system utilizing off chip bitcode lookup for adaptive keeper sizing, in accordance with an embodimentof the present invention.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0025] An invention is disclosed for adaptive keeper transistor sizingin dynamic circuits based on fused process corner data. Broadlyspeaking, embodiments of the present invention adjust the effectivekeeper transistor size by enabling additional keeper transistors basedon the characteristics of the particular dynamic circuit (i.e., Processcorner). As described in greater detail below, these characteristics aredetermined by examining data electrically programmed onto the die. Inthe following description, numerous specific details are set forth inorder to provide a thorough understanding of the present invention. Itwill be apparent, however, to one skilled in the art that the presentinvention may be practiced without some or all of these specificdetails. In other instances, well known process steps have not beendescribed in detail in order not to unnecessarily obscure the presentinvention.

[0026] As mentioned above, embodiments of the present invention adjustthe effective size of the keeper transistor according to the processconditions of the die. For example, at faster process corners theleakage current of the pull down transistors is high. As a result,embodiments of the present invention increase the strength of the keepertransistor to prevent unintentional discharging of the internal dynamicnode. However, at nominal process corners, the leakage current of thepull down transistors generally is lower than at faster process corners.Hence, the keeper size is reduced to allow faster operation at normalconditions. In this manner, embodiments of the present invention allowwider and faster dynamic OR circuits, thereby enabling fastermicroprocessor operation.

[0027]FIG. 2 is a schematic diagram showing an exemplary dynamic wide ORcircuit 200, in accordance with an embodiment of the present invention.The dynamic wide OR circuit 200 includes a precharge p-channeltransistor 102, having a first terminal coupled to VDD, a secondterminal coupled to an internal dynamic node 110, and a gate coupled toa clock signal 108. In addition, a plurality of evaluation transistors104 a-104 c is included. Each evaluation transistor 104 a-104 c includesa first terminal coupled to the internal dynamic node 110 and a secondterminal coupled to a first terminal of transistor 106. In addition, thegate of each evaluation transistor 104 a-104 c is coupled to an inputIn₀, In₁, and In₂, respectively. A second terminal of transistor 106 iscoupled to ground and the gate of transistor 106 is coupled to the clocksignal 108. Although FIG. 2 illustrates an OR circuit, it should benoted that the evaluation transistors can be configured to form anylogic circuit as desired by the circuit developer.

[0028] For completeness, the operation of the dynamic OR circuit will bedescribed. As described above, the dynamic wide OR circuit 200 operatesusing a precharge phase and an evaluation phase. During the prechargephase the clock signal 108 is LOW, which turns transistor 106 OFF andturns the precharge transistor 102 ON, allowing current to flow from VDDto the internal dynamic node 110. As a result, a precharge is providedto the internal dynamic node 110, which goes HIGH. Because transistor106 is OFF, the internal dynamic node 110 stays high during theprecharge phase regardless of the state of the evaluation transistors104 a-104 c.

[0029] During the evaluation phase the clock signal 108 is HIGH. Hence,transistor 106 is ON and the precharge transistor 102 is OFF, whichallows current to flow from the internal dynamic node 110 to groundbased on the state of the evaluation transistors 104 a-104 c. The stateof each evaluation transistor 104 a-104 c depends on the state of theinput In₀, In₁, and In₂ coupled to the gate of the particular evaluationtransistor 104 a-104 c. As can be seen in the example of FIG. 2, whenthe input In₀, In₁, and In₂ of any evaluation transistor 104 a-104 c isHIGH, the evaluation transistor 104 a-104 c turns ON and allows currentto flow from the internal dynamic node 110 to ground through transistor106. As a result, the output 112 will be LOW.

[0030] However, when all the inputs In₀, In₁, and In₂ of the evaluationtransistors 104 a-104 c are LOW, all the evaluation transistors 104a-104 c are OFF and the internal dynamic node 110 is allowed to stayHIGH, resulting in a HIGH at the output 112. As mentioned above, theevaluation transistors 104 a-104 c leak. Thus, when all the inputs In₀,In₁, and In₂ of the evaluation transistors 104 a-104 c are LOW, aleakage current is still allowed to flow from the internal dynamic node110 to ground though transistor 106.

[0031] Embodiments of the present invention utilize an adaptive keepercircuit 202 to compensate for the leakage current through the evaluationtransistors 104 a-104 c. The adaptive keeper circuit 202 includes aninverter 204 having an input coupled to the internal dynamic node 110and an output coupled to the gate of a first keeper transistor 206. Afirst terminal of the first keeper transistor 206 is coupled to VDD anda second terminal is coupled to the internal dynamic node 110. Inaddition, the output of the inverter 204 is coupled to the gate of asecond keeper transistor 208, which includes a first terminal coupled toVDD and a second terminal coupled to a first terminal of a feedbacktransistor 210. The second terminal of the feedback transistor 210 iscoupled to the internal dynamic node 110, and the gate of the feedbacktransistor 210 is coupled to a feedback bit 212.

[0032] Embodiments of the present invention vary the effective size ofthe keeper transistor by adding or subtracting the second keepertransistor 208 to the first keeper transistor 206. Control is providedby the feedback bit 212, which is coupled to the gate of the feedbacktransistor 210. For example, during operation at a normal processcorner, the feedback bit 212 is HIGH, which turns the feedbacktransistor 210 OFF. When the feedback transistor 210 is OFF, the pathfrom the second keeper transistor 208 to the internal dynamic node 110is disabled. As a result, the second keeper transistor 208 is not addedto the first keeper transistor 206. However, during operation at a fastprocess corner, the feedback bit 212 is LOW, which turns the feedbacktransistor 210 ON. Consequently, current is allowed to flow from thesecond keeper transistor 208 to the internal dynamic node 110. As aresult, the second keeper transistor 208 is added to the first keepertransistor 206, effectively increasing the size of the keepertransistor.

[0033] Thus, the keeper circuit 202 can be used to keep the internaldynamic node 110 HIGH when all the evaluation transistors 104 a-104 care OFF. When the internal dynamic node 110 is HIGH, the input of theinverter 204 is HIGH, resulting in a LOW at the output of the inverter204. The LOW at the output of the inverter 204 turns ON both the firstkeeper transistor 206 and the second keeper transistor 208.Consequently, the first keeper transistor 206 allows current to flowinto the internal dynamic node 110 from VDD. In addition, depending onthe state of the feedback transistor 210, the second keeper transistor208 may allow additional current to flow into the internal dynamic node110 from VDD. That is, when the feedback transistor 210 is ON, thesecond keeper transistor allows additional current is allowed to theinternal dynamic node 110. However, when the feedback transistor 210 isOFF, the path from the second keeper transistor 208 to the internaldynamic node 110 is disabled, and current from the second keepertransistor 208 is not added to the internal dynamic node 110.

[0034] When the internal dynamic node is LOW, for example because of anevaluation transistor 104 a-104 c being ON, the keeper circuit 202 turnsOFF. Specifically, when the internal dynamic node 110 is LOW, the inputof the inverter 204 is LOW, resulting in a HIGH at the output of theinverter 204. The HIGH at the output of the inverter 204 turns OFF boththe keeper transistors 206 and 208, which prevents current from flowinginto the internal dynamic node 110 from VDD, regardless of the state ofthe feedback transistor 210.

[0035] Additional keeper transistors can be utilized in the keepercircuit 202 of the embodiments of the present invention to provideincreased keeper size variation. For example, FIG. 3 is a schematicdiagram showing a keeper circuit 202′ having three keeper transistorpaths, in accordance with an embodiment of the present invention. Inthis case, control is provided by two feedback bits fb₀ 212 and fb₁ 304,each coupled to the gate of feedback transistor 210 and feedbacktransistor 302, respectively.

[0036] The additional keeper transistor paths operate in a mannersimilar to that described with respect to FIG. 2. Specifically, when thefeedback bit fb₀ 212 is HIGH, feedback transistor 210 OFF, whichdisables the path from the second keeper transistor 208 to the internaldynamic node 110. Similarly, when the feedback bit fb₁ 304 is HIGH,feedback transistor 302 OFF, which disables the path from the thirdkeeper transistor 300 to the internal dynamic node 110. As a result,neither the second keeper transistor 208 nor the third keeper transistor300 is added to the first keeper transistor 206.

[0037] When the feedback bit fb₀ 212 is LOW, feedback transistor 210 ON,which allows additional current to flow from the second keepertransistor 208 to the internal dynamic node 110. Similarly, when thefeedback bit fb₁ 304 is LOW, feedback transistor 302 ON, which alsoallows additional current to flow from the second keeper transistor 208to the internal dynamic node 110. As a result, both the second keepertransistor 208 and the third keeper transistor 302 are added to thefirst keeper transistor 206, thus effectively increasing the size of thekeeper transistor. As can be appreciated, various combinations of keepertransistors 208 and 300 can be added to the first keeper transistor 206,depending on the states of the feedback bits fb₀ 212 and fb₁ 304. Forexample, when feedback bit fb₀ 212 is HIGH and fb₁ 304 is LOW, the thirdkeeper transistor 300 will be added to the first keeper transistor 206,while the second keeper transistor 208 will not be added to the firstkeeper transistor 206.

[0038] As above, when the internal dynamic node 110 is HIGH, the inputof the inverter 204 is HIGH, resulting in a LOW at the output of theinverter 204. The LOW at the output of the inverter 204 turns ON all thekeeper transistors 206, 208, and 300. Consequently, the first keepertransistor 206 allows current to flow into the internal dynamic node 110from VDD and, depending on the state of the feedback bits fb₀ 212 andfb₁ 304, additional current may be allowed to flow into the internaldynamic node 110 from VDD, as described above.

[0039] When the internal dynamic node is LOW, the keeper circuit 202′turns OFF. That is, when the internal dynamic node 110 is LOW, the inputof the inverter 204 is LOW, resulting in a HIGH at the output of theinverter 204. The HIGH at the output of the inverter 204 turns OFF allthe keeper transistors 206, 208, and 300, which prevents current fromflowing into the internal dynamic node 110 from V_(DD), regardless ofthe state of the feedback bits fb₀ 212 and fb₁ 304.

[0040] As discussed above, embodiments of the present invention can beutilized with as many additional keeper transistors as required by theparticular circuit configuration. Moreover, each keeper transistor canitself be different in size to other keeper transistors. For example,the keeper transistors can be weighted in a binary fashion such that thesecond keeper transistor 208 is twice as large as the first keepertransistor 206, and the third keeper transistor 300 can be twice aslarge as the second keeper transistor 206. This also applies to thefeedback transistors, which can be scaled proportionately to thecorresponding keeper transistor. In this manner, each keeper transistorpath, which includes a keeper transistor and the feedback transistorcoupled to it, can be scaled to obtain a greater number of keeper sizecombinations using fewer feedback bits.

[0041] Embodiments of the present invention vary the effective size ofthe keeper transistor based on the process corner of the die. This isaccomplished by changing the state of the feedback bits based on theprocess corner of the die. FIG. 4 is a block diagram showing a die 400having adaptive keeper sizing capabilities, in accordance with anembodiment of the present invention. As shown in FIG. 4, the die 400includes an electrical fuse bank 402 and a test processor unit 404 inelectrical communication with the electrical fuse bank 402. The testprocessor unit 404 is also in communication with a plurality of dynamiccircuits 200 a-200 c, each having adaptive keeper circuits. Althoughthree dynamic circuits 200 a-200 c are illustrated in FIG. 4, it shouldbe noted that any number of dynamic circuits can be included on the die400 and placed in communication with the test processor unit 400.

[0042] Broadly speaking, the test processor unit 400 of the embodimentsof the present invention determines bit codes for the feedback bits ofthe die 400, and provides these codes to each dynamic circuit 200 a-200c requiring feedback bit data. The embodiments of the present inventionutilize process corner data provided by chip manufactures to scale thekeeper circuit sizes for dynamic circuits on the die 400. In particular,during chip manufacturing, globally occurring process variation isdetermined for each die 400. Generally, this is performed by the chipmanufacturer and is programmed on the die 400 using the electrical fusebank 402.

[0043] The electrical fuse bank 402 comprises a plurality of fuses,which can be blown in a particular configuration to indicate the processcorner in which the particular die 400 tested. For example, if the die400 is tested and found to be in a fast fast (ff) process corner, the ffprocess corner can be indicated by blowing a particular fuseconfiguration in the electrical fuse bank 402. It should be noted thatthe actual fuses utilized in the electrical fuse bank 402 can compriseany type of fuse such as flash, EPROM, or any other type of fuse. Asmentioned above, generally the chip manufacturer programs the processcorner data onto the die 400. However, it should be noted that theprocess corner data can be tested and programmed onto the die 400 atanytime prior to use.

[0044] In operation, the test processor unit 404 reads the configurationof the fuses in the electrical fuse bank 402 to determine the processcorner for particular die 400. Once read, the test processor unit 404translates the fuse information into a bit code that indicates theprocess corner of the die 400. Generally, the translation can beperformed utilizing a lookup table that cross-indexes fuse data withcorresponding bit codes. For example, if a particular set of dies areclassified into three process corners such as fast fast (ff), slow fast(sf), and slow slow (ss), an exemplary bit code may be: ff 00 sf 01 ss10

[0045] Hence, if the electrical fuse bank 402 of the die 400 included afuse configuration that indicated a sf process corner, the testprocessor unit 404 will, in this example, translate the sf processcorner data into the bit code “01.” The test processor unit 404 thendistributes the translated bit code to the plurality of dynamic circuits200 a-200 c throughout the die 400. Generally, each bit in the bit codecorresponds to a particular feedback bit. For example, the above bitcode “01” can indicate that feedback bit fb₀ is HIGH and feedback bitfb₁ is LOW, in FIG. 2. In this manner, each dynamic circuit 200 a-200 cof the die 400 will have its keeper transistor sized appropriately forthe process corner of the die 400.

[0046] In addition to being stored on the die 400, as illustrated inFIG. 4, the bit code mapping can be obtained off chip. FIG. 5 is a blockdiagram showing a system 500 utilizing off chip bit code lookup foradaptive keeper sizing, in accordance with an embodiment of the presentinvention. As shown in FIG. 5, the system 500 includes an adaptivekeeper size chip 400, as discussed above with respect to FIG. 4. Inaddition, the adaptive keeper size chip 400 is in communication with alookup processor 502. The lookup processor 502 can be any processor thatis capable of translating the fuse data into bit codes for use in theadaptive keeper size chip 400. For example, the lookup processor 502 canbe a central processing unit (CPU) for the system 500, or a dedicatedlookup processor.

[0047] In the system 500, the test processor unit of the adaptive keepersize chip 400 uses the lookup processor 502 to translate the fuseconfiguration data into bit codes for use in the dynamic circuits of theadaptive keeper size chip 400. In particular, once the test processorunit of the adaptive keeper size chip 400 reads the fuse data from theelectrical fuse bank, the test processor unit sends a request to thelookup processor 502. The request generally includes the fuse data, andindicates the test processor unit requires the corresponding bit codefor the fuse data. In response, the lookup processor 502 translates thefuse data into a corresponding bit code, for example, by performing alookup operation, as described above. Thereafter, the lookup processor502 transmits the requested bit code to the test processor unit of theadaptive keeper size chip 400. Since the translation is performed offchip using the lookup processor 502, the translation process can besoftware based. In this manner, a user can easily program thetranslation operation that the lookup processor 502 will perform, thusgiving the user increased flexibility.

[0048] Embodiments of the present invention may be implemented using anytype of integrated circuit logic, state machines, or software drivencomputer-implemented operations. By way of example, a hardwaredescription language (HDL) based design and synthesis program may beused to design the silicon-level circuitry necessary to appropriatelyperform the data and control operations in accordance with oneembodiment of the present invention.

[0049] The invention may employ various computer-implemented operationsinvolving data stored in computer systems. These operations are thoserequiring physical manipulation of physical quantities. Usually, thoughnot necessarily, these quantities take the form of electrical ormagnetic signals capable of being stored, transferred, combined,compared, and otherwise manipulated. Further, the manipulationsperformed are often referred to in terms, such as producing,identifying, determining, or comparing.

[0050] Any of the operations described herein that form part of theinvention are useful machine operations. The invention also relates to adevice or an apparatus for performing these operations. The apparatusmay be specially constructed for the required purposes, or it may be ageneral purpose computer selectively activated or configured by acomputer program stored in the computer. In particular, various generalpurpose machines may be used with computer programs written inaccordance with the teachings herein, or it may be more convenient toconstruct a more specialized apparatus to perform the requiredoperations.

[0051] Although the foregoing invention has been described in somedetail for purposes of clarity of understanding, it will be apparentthat certain changes and modifications may be practiced within the scopeof the appended claims. Accordingly, the present embodiments are to beconsidered as illustrative and not restrictive, and the invention is notto be limited to the details given herein, but may be modified withinthe scope and equivalents of the appended claims.

What is claimed is:
 1. An adaptive keeper circuit, comprising: a firstkeeper transistor having a first terminal in electrical communicationwith a power supply and a second terminal in electrical communicationwith an internal dynamic node; a second keeper transistor configured inparallel to the first keeper transistor, the second keeper transistorhaving a first terminal in electrical communication with the powersupply; and a feedback bit line configured to control current flowbetween the second keeper transistor and the internal dynamic node basedon a state of the feedback bit line, the state of the feedback bit linebeing based on a process corner characteristic of the die.
 2. Anadaptive keeper circuit as recited in claim 1, further comprising afeedback transistor having a first terminal in electrical communicationwith the second keeper transistor, a second terminal in electricalcommunication with the internal dynamic node, and a gate coupled to thefeedback bit line.
 3. An adaptive keeper circuit as recited in claim 2,wherein the feedback transistor controls current flow between the secondkeeper transistor and the internal dynamic node based on a state of thefeedback bit line.
 4. An adaptive keeper circuit as recited in claim 1,further comprising a plurality of incremental keeper transistors, eachincremental keeper transistor configured in parallel to the first keepertransistor, each incremental keeper transistor having a first terminalin electrical communication with the power supply.
 5. An adaptive keepercircuit as recited in claim 4, further comprising a plurality offeedback bit lines each corresponding to a particular incremental keepertransistor of the plurality of incremental transistors, each feedbackbit line configured to control current flow between the correspondingincremental keeper transistor and the internal dynamic node based on astate of the feedback bit line.
 6. An adaptive keeper circuit as recitedin claim 5, wherein the state of each feedback bit line of the pluralityof feedback bit lines is based on a process corner characteristic of thedie.
 7. An adaptive keeper circuit as recited in claim 5, furthercomprising a plurality of feedback transistors that control current flowbetween corresponding incremental keeper transistors of the plurality ofincremental keeper transistors and the internal dynamic node.
 8. Anadaptive keeper circuit as recited in claim 7, wherein a gate of eachfeedback transistor of the plurality of feedback transistors is coupledto a corresponding bit line of the plurality of bit lines.
 9. Asemiconductor die having adaptive keeper logic, comprising: a pluralityof dynamic circuits, each dynamic circuit including an adaptive keepercircuit capable of being adjusted based on a bit code; a process cornerdatabank having process corner data that indicates a process corner ofthe semiconductor die; and a test processor unit in communication withthe process corner databank and the plurality of dynamic circuits, thetest processor unit being capable of obtaining process corner data fromthe process corner databank, the test processor unit further beingcapable of providing a bit code based on the process corner data to theplurality of dynamic circuits.
 10. A semiconductor die as recited inclaim 9, wherein the process corner databank is a fuse bank having aplurality of fuses, wherein a configuration of the plurality of fusesindicates a process corner of the semiconductor die.
 11. A semiconductordie as recited in claim 10, wherein each adaptive keeper circuitincludes at least one feedback bit line that receives a portion of thebit code, the feedback bit line controlling current flow to an internaldynamic node.
 12. A semiconductor die as recited in claim 11, whereineach adaptive keeper circuit further includes a first keeper transistorand at least one secondary keeper transistor in parallel with the firstkeeper transistor, the first keeper transistor and the secondary keepertransistor being in electrical communication with a power supply, thefirst keeper transistor further being in electrical communication withan internal dynamic node.
 13. A semiconductor die as recited in claim12, wherein each adaptive keeper circuit further includes at least onefeedback transistor in electrical communication with the at least onesecondary transistor, the feedback transistor controlling current flowbetween the secondary transistor and the internal dynamic node.
 14. Asemiconductor die as recited in claim 13, wherein the at least onefeedback transistor controls current flow between the secondarytransistor and the internal dynamic node based on a state of thefeedback bit line.
 15. A semiconductor die as recited in claim 9,wherein the test processor unit translates the process corner data intothe bit code using a lookup function.
 16. A semiconductor die as recitedin claim 9, further comprising a lookup processor that receives processcorner data from the test processor unit and provides a correspondingbit code to the test processor unit based on the received process cornerdata.
 17. A method for optimizing a keeper circuit for use in a dynamiccircuit, comprising the operations of: obtaining process corner data fora die from a databank present on the die; translating the process cornerdata into a bit code, the bit code indicating a process corner of thedie; and adding particular secondary keeper transistors to a firstkeeper transistor, the particular secondary keeper transistors beingselected using the bit code.
 18. A method as recited in claim 17,wherein secondary keeper transistors are added to the first keepertransistor utilizing corresponding feedback transistors, each feedbacktransistor having a gate coupled to a bit of the bit code.
 19. A methodas recited in claim 18, wherein the databank is an electrical fuse bankcomprising a plurality of fuses, the process corner data beingrepresented by a particular fuse configuration of the plurality offuses.
 20. A method as recited in claim 19, wherein each secondarykeeper transistor provides current to an internal dynamic node based ona state of the bit code.